Bug 05 - Debug Module Authentication Hardwired to 1 (Unauthenticated JTAG Debug)
Legacy reference: Bug #2 in the working set
Security feature bypassed
RISC-V Debug Specification v0.13 password authentication - the mandatory dmstatus.authenticated gate
Attack type
Type 2 - physical attacker with JTAG access
Finding
dmstatus.authenticated is hardwired to 1'b1 with the comment “no authentication
implemented”. The AuthData CSR (address 0x30, defined in dm_pkg.sv:80) is declared but
never handled in any read/write case statement - writes are silently dropped, reads return 0:
// dm_csrs.sv:231
dmstatus.authenticated = 1'b1; // No authentication implemented
Location or code reference
- hw/vendor/pulp_riscv_dbg/src/dm_csrs.sv:231 -
dmstatus.authenticated = 1'b1;hardwired - hw/vendor/pulp_riscv_dbg/src/dm_pkg.sv:80 - AuthData CSR defined but never handled
New Tools
No automated detection tool. Manual RTL inspection: a grep for “authenticated” across the vendor subtree returns only the constant assignment; a grep for “AuthData” confirms the CSR address is never handled.
AI Tools
No.
LLM
No.
LLM Details
PLACEHOLDER - to be completed (model name/version, parameters, download link or API endpoint).
Online LLM Details
PLACEHOLDER - to be completed (input/output/total token counts, verification script).
LLM Prompts
PLACEHOLDER - to be completed (complete prompt, full model response, step-by-step explanation).
Detection method
Manual RTL inspection (constant-assignment grep). Confirmed on the actual OpenTitan RTL:
dm_csrs_tb.sv instantiates the real dm_csrs.sv with its genuine dependency chain
(dm_pkg, prims) and performs a DMI read of DMSTATUS with no AuthData handshake -
the response carries authenticated=1 (see testbench/logs/rtl-test-simulation.log:
*** BUG #2 CONFIRMED on actual OpenTitan RTL ***, data=0x000c0c82, bit 10 set).
Security impact
Any entity with JTAG/DMI access obtains full, unauthenticated debug control: halt/resume harts, read/write all CSRs, system-bus access, and arbitrary code execution via the program buffer. In TEST_UNLOCKED / DEV / RMA lifecycle states (where LC gating is open), a ~$30 JTAG probe (FT2232H) suffices for complete device compromise - key extraction, firmware modification, code injection.
Adversary profile
Type 2 - physical attacker with a JTAG probe. Requires physical possession and standard debug hardware (e.g. FT2232H + OpenOCD). No credentials of any kind.
Proposed mitigation
// Implement a proper authentication FSM:
dmstatus.authenticated = auth_state_q; // not 1'b1
// Add AuthData write handler: compare write against provisioned secret
CVSSv3.1 score and severity
6.8 - MEDIUM
CVSSv3.1 Details
CVSS:3.1/AV:P/AC:L/PR:N/UI:N/S:C/C:H/I:H/A:H
- AV: Physical - requires JTAG connection to the device
- AC: Low - no negotiation, no timing constraints
- PR: None - no password, no credentials
- S: Changed - crosses from debug port into all SoC domains
- C/I/A: High - full register/memory read-write, code execution
Attachment links
Located in this repository (GitHub is the cloud storage for the submission):